Vlsi Design of Low Transition Low Power Test Pattern Generator Using Fault Coverage Circuits

Now a day’s highly integrated multi layer board with IC’s is virtually impossible to be accessed physically for testing. The major problem detected during testing a circuit includes test generation and gate to I/O pin problems. In design of any circuit, consuming low power and less hardware utilization is an important design parameter. Therefore reliable testing methods are introduced which reduces the cost of the hardware required and also power consumed by the device. In this project a new fault coverage test pattern generator is generated using a linear feedback shift register called FC-LFSR which can perform fault analysis and reduces the total power of the circuit. In this test, it generates three intermediate patterns between the random patterns which reduces the transitional activities of primary inputs so that the switching activities inside the circuit under test will be reduced. The test patterns generated are applied to c17 benchmark circuit, whose results with fault coverage of the circuit being tested. The simulation for this design is performed using Xilinx ISE software using Verilog hardware description language.